1. Field of the Invention
The present invention relates generally to a digital-analog converter (DAC), and more particularly, to a current-mode DAC capable of prospective correction.
2. Description of the Related Art
Recently, as the high-speed wireless local area network (WLAN) and the digital television are highly developed, the specification of the mixed-signal blocks with the applications of requiring high speed and high resolution for system is higher and higher. The requirement for the specification of the DAC is farther strict. Among the high-specification DACs, the current-mode DAC is the most appropriate.
Where the non-ideal effect is well-known, during the high-speed operation, the harmonic interference results in worse performance to further limit the spurious-free dynamic range (SFDR) of the DAC. Generally speaking, such error not only results from the mismatch of current source but the impedance generated due to the limited parasitic effect of the switching current source unit. Under the circumstances, further installing a transistor between the current source and the switch, as a conventional way, to improve that the impedance is insufficient to cause a second-harmonic wave while the signal is inputted under high frequency.
In addition, an accurate DAC design must have the static non-linear value (due to the random error of the manufacturing process) of its internal current source cell within the confined specification. In the prior art, a plurality of the current source cells are arranged in array, where the yield rate of the random error can define the gate area of the transistor included in each current source, and the gate area is subject to being greater, such that the parasitic effect of the internal contacts increases to lower the high-frequency SFDR. This problem has become a big issue for the high-speed operation. Although someone proposed the internal-inherent accuracy degree based on the gradient effect of the manufacturing-process error for cutting it into several arrays having symmetric centers in such a way that the equalization of the error is effected to decrease some gate area, there is still a drawback of insufficient accuracy of correction.